发明名称 |
CIRCUIT FOR ESTABLISHING ACCURATE SAMPLE TIMING |
摘要 |
<p>"Circuit for Establishing Accurate Sample Timing" In order to establish accurate sample timing in a digital demodulator which forms part of an orthogonally multiplexed parallel data transmission system, two second-order PLLs are arranged after a demodulating section of the digital demodultor so as to receive baseband signals of corresponding pilot channels. The two second-order PLLs each includes an integrator. These integrators apply the outputs thereof to a subtracter which applies the subtraction result to a voltage-controlled oscillator in order to establish the accurate sample timing.</p> |
申请公布号 |
CA1224541(A) |
申请公布日期 |
1987.07.21 |
申请号 |
CA19840462211 |
申请日期 |
1984.08.31 |
申请人 |
NEC CORPORATION |
发明人 |
AOYAGI, HIDEHITO;HIROSAKI, BOTARO |
分类号 |
H04L7/00;H04J11/00;H04L7/02;H04L25/03;H04L27/22;H04L27/26;H04L27/34;H04L27/38;(IPC1-7):H04J11/00;H04J1/02;H04L27/14 |
主分类号 |
H04L7/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|