| 摘要 |
PURPOSE:To easily attain an optimum architecture by providing a decoding part which decodes an instruction supplied from the external to convert it to an internal instruction and supplies this internal instruction to an instruction executing part. CONSTITUTION:Both processors 1a and 1b adopt the microprogram control system and use the same operating part 3, and respective decoding parts 5a and 5b, microprogram storage parts 7a and 7b, and bus control parts 9a and 9b as the other constituting parts are made different from each other in accordance with respective architectures. The instruction stored in a memory data register 17 is supplied to the instruction buffer register 19 of the decoding part 5 and the destination bus (DBUS) 4 of the operating part 3. The instruction stored in the instruction buffer register 19 is supplied to a decode logic 21 and is converted to a corresponding internal instruction and is supplied to an internal instruction register 23. Thus, only the decoding part is changed in accordance with supplied instructions to attain easily the different architectures of processors.
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