| 摘要 |
PURPOSE:To improve multilayer interconnection reliability and to enhance semiconductor integrated circuit integration density by a method wherein a pattern is formed as required in a part of a lower wiring on a semiconductor substrate with the other part thereof remaining unaffected, an interlayer insulating film is grown with a voltage, opposite in polarity to the voltage of the substrate, applied to the lower wiring, a apart of the lower wiring is removed by etching, and then another insulating film is grown. CONSTITUTION:A metal film is grown to be developed into a lower metal wiring on a semiconductor substrate 10 already provided with required circuit elements. The metal films is then exposed to etching for the formation of a lower metal wiring 11 of a required pattern. The semiconductor substrate 10 is installed on a lower electrode 3, is connected to a high-frequency oscillator 7, and the lower metal wiring 11 is connected to a voltage step-down unit 8. They are placed as is in a vacuum chamber 1. Pressure is maintained at a prescribed value and plasma CVD reaction is caused to take place. Subsequently, a part 11a of the lower metal wiring 11 is selectively removed, a new insulating film 13 is grown thin for the establishment of insulation for the portions involved, and then an upper metal wiring 14 is formed by a conventional method. With the circuit being designed as such, the upper metal wiring 14 is protected from step-caused disconnection or short-circuiting due to what may be retained after etching.
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