发明名称 CMI CODE CONVERTER
摘要 PURPOSE:To obtain a CMI code output without any whisker-like pulse by forming a double frequency clock with simple constitution from a signal retarding a clock input and the original clock signal. CONSTITUTION:A Q output of a FF 7 and a Q output of a FF 5 are inputted to a gate circuit G6, which encodes a level '1' at a terminal IN into '00', '11' alternately. A gate circuit G4 outputs a code '01' when the level of a terminal IN is logical 0. A gate circuit G3 outputs a coded '10' to a request of the violation of code rules. A gate circuit G5 synthesizes outputs of the circuits G4 and G3 and encodes the signal '01' for a signal '0' at the terminal IN and the signal '10' for a signal '0' at a terminal CRV. The output of the circuit G6 and the Q output of a FF 6 are synthesized by a gate circuit G7. A CMI code output is obtained from an output terminal OUT. Thus, a CMI code output having no whisker-like pulse is obtained.
申请公布号 JPS62163440(A) 申请公布日期 1987.07.20
申请号 JP19860004107 申请日期 1986.01.14
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 SANADA TAKESHI
分类号 H03M5/06;H04L25/49 主分类号 H03M5/06
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