发明名称 MANUFACTURE OF GALLIUM ARSENIDE INTEGRATED CIRCUIT
摘要 PURPOSE:To make it possible to equalize substantially the electric characteristic of GaAs MESFET formed in two directions and to increase the freedom in designing a mask by a method wherein an n-type GaAs crystal layer is etched by a chemical etching liquid before the selective epitaxial growth of an n-type GaAs layer of high concentration. CONSTITUTION:A plurality of MESFETs wherein n-type GaAs crystal layers 12 and 13 formed on the (100) surface of a semiinsulative GaAs substrate 11 are made to be operating regions, a silicide layer and another 14 and 15 provided thereon are made to be Schottky barrier junction gate electrodes and n-type GaAs layers of high concentration made to grow epitaxially on the opposite sides thereof are made to be source and drain regions, are formed, and they are connected organically with one another. In an integrated circuit formed in this way, the n-type GaAs crystal layers 12 and 13 in the source and drain regions are etched by an anisotropic chemical etching liquid before the n-type GaAs layers of high concentration are made to grow epitaxially, and thereby MESFET 210 wherein a gate electrode is formed parallel to a (011) surface and MESFET 220 wherein a gate electrode is formed parallel to a (01-1) surface are made substantially equal to each other in terms of electric characteristics.
申请公布号 JPS62163377(A) 申请公布日期 1987.07.20
申请号 JP19860005603 申请日期 1986.01.13
申请人 NEC CORP 发明人 KATANO FUMIAKI
分类号 H01L21/306;H01L21/205;H01L21/302;H01L21/338;H01L29/80;H01L29/812 主分类号 H01L21/306
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