| 摘要 |
PURPOSE:To detect a phase error by producing a sampling clock having a frequency (n) times as high as that of a data signal to sample the data signal and deciding the output of a sampling circuit based on a prescribed deciding pattern. CONSTITUTION:A phase synchronizing circuit 1 delivers a sampling clock signal a2 having a frequency (n) times as high as that of a data signal a1 and a signal a3 having a data cycle synchronous with the signal a1 after the data a1 read out of a recording medium, etc., is inputted. A sampling circuit 2 samples the signal a1 by the rise timing of the signals a2 and outputs an output signal a4. This signal a4 is supplied to shift registers D-FF4-9 of a decoding circuit respectively and the output signals of FF4-9 are inputted to a ROM 10. While a deciding pattern produced based on the characteristics proper to the recording medium and a recording system is written previously to the ROM 10. The output signal of the ROM 10 is inputted to a D-FF group 11. Then it is possible to output a data deciding signal a15 and a phase error detecting signal a16 through the group 11.
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