发明名称 DATA TRANSFER SYSTEM
摘要 PURPOSE:To perform parallel processings of data transmission and reception with an inexpensive device by transmitting the first data at an accurate timing and receiving the second data at a timing an extent of offset behind the timing of the first data. CONSTITUTION:If a microcomputer (MPU) detects the input of the second data while transmitting the first data, the extent of deviation between timings of both data is detected. An optimum extent of offset nearest to this extent of deviation is selected from plural extents of offset stored in an incorporated ROM and is inputted to an incorporated RAM. This processing is completed before the following bit of the first bit is transmitted after detection of the second data. The following bit of the first data is transmitted and one bit of the second data is received at the timing the selected extent of offset after, and this operation is repeated, and the transmission of the first data is completed when one-byte components of data are transmitted, and the reception of the second data is completed when one-byte components of data are received thereafter.
申请公布号 JPS62164151(A) 申请公布日期 1987.07.20
申请号 JP19860006755 申请日期 1986.01.16
申请人 FUJITSU LTD 发明人 TAJIMA SHIYUUTAROU
分类号 G06F13/00 主分类号 G06F13/00
代理机构 代理人
主权项
地址