| 摘要 |
<p>PURPOSE:To contrive access regardless of refreshing and to ensure a high-speed operation of a semiconductor memory, by holding data read out of a dynamic RAM in a static RAM and separating the dynamic RAM from an input/output signal line. CONSTITUTION:Data are read out to a bit line BL and the inverse of BL of a dynamic RAM part 6 by a load address decoder 8. Then the selection signal Yi of a column address decoder 14 is excited by a timing signal phiS3. A MOSFET 15 is turned on and the data on the BL and the inverse of BL are sent to output signal lines I/Oi and the inverse of I/Oi via MOSFETs 13 and 15 respectively. At the same time, those data are stored in a static memory cell 18 and held there. Then the FET 13 is turned off by the signal phiS3 and the part 6 is separated from the I/Oi and the inverse of I/Oi. Thus access is possible regardless of refreshing and a high-speed operation is ensured for a semiconductor memory.</p> |
