发明名称 MEMORY INFORMATION READING CIRCUIT
摘要 PURPOSE:To prevent detecting error of read data by checking simultaneously both facts that the differential signal of a read analog signal has a level higher than the prescribed negative threshold value and that the differential signal delayed by a prescribed delay time has a level higher than the prescribed posi tive threshold value. CONSTITUTION:An analog signal 101 reproduced by a reading optical head 1 is supplied to a differentiating circuit 3 via an amplifying circuit 2. A differen tial signal 102 is supplied to delay circuits 4 and 4a containing the delay lines having the total delay time Td as well as to a comparator 7. A delay differen tial signal 103 obtained by delaying the signal 102 by Td/2 and a delay differen tial signal 104 delayed by Td are supplied to both comparators 5 and 6 respec tively. The coincidence conditions are secured by an AND circuit 8 between a positive level signal 106 and a negative level signal 107. Then a level signal 108 is supplied to the D input of a D type FF 9 and a peak signal 105 is sup plied to the clock input of the FF 9. A read digital signal 109 can be output through the coincidence conditions secured between both signals 105 and 108. Thus a detecting error of a read data can be avoided.
申请公布号 JPS62164275(A) 申请公布日期 1987.07.20
申请号 JP19860005651 申请日期 1986.01.14
申请人 NEC CORP 发明人 TANAHASHI YUTAKA
分类号 G11B20/10 主分类号 G11B20/10
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