| 摘要 |
PURPOSE:To identify an interruption requesting peripheral device by a CPU in a short time by constituting a system so that the interruption requesting peripheral device which receives first an interruption permission signal from the CPU closes a gate circuit, and the transfer of the signal is terminated, and a priority for a transfer order is set. CONSTITUTION:An interruption flag 17 is set at the peripheral device by an interruption factor, and an interruption request signal is transferred to the CPU from the peripheral device, and the interruption permission signal is returned from the CPU. Since the flag 17 has been set, the driver of a peripheral device address generation part 14 is started up through an AND circuit 1, and an address N is sent to a bus 13. Also, an AND circuit 15 is closed, and the interruption permission signal is not sent to the next-order peripheral device. The CPU, by identifying a bit of address information after the sending of the interruption permission signal on the bus 13, can easily identify the interruption requesting peripheral device. The interruption requesting peripheral device which has received the interruption permission signal corresponding to the priority order occupies the bus 13, and performs a data transfer through a driver receiver 16. |
