发明名称 MANUFACTURE OF SEMICONDUCTOR DEVICE
摘要 PURPOSE:To contrive the prevention of disconnection of the lower metal interconnection layer and the improvement of etching efficiency by a method wherein a laminate consisting of a plurality of layers of insulating layers laminated between the upper and lower metal interconnection layers is etched at a time by a reactive ion etching method. CONSTITUTION:An Si nitriding layer 102, a Zr oxide layer (coupler layer) 103, a polyimide layer 104, an Si oxide layer 105 and a P-type resist pattern layer 106 are formed on an Al interconnection layer 101 arranged on an Si substrate 100. First, the layer 105 is etched by a reactive anisotropic ion etching method. Then, an etching is performed on the layer 104 by an isotropic etching method. Hereby, as a protrusion part 105a of the Si oxide layer 105 is protruded in an overhang form. Subsequently, the layer 103 and the layer 102 are etched. In these etchings, as the protrusion 105 is used as a mask and the start of etching to the layer 102 just under the protrusion is delayed, the final etched shape is formed into a two-stage. According to the above method, an etching efficiency is improved because the laminate is etched at a time and also, the disconnection of the Al interconnection layer whose Al interconnection is adhered on the layer 105 is prevented because the layer 105 has no overhang.
申请公布号 JPS62162345(A) 申请公布日期 1987.07.18
申请号 JP19860003490 申请日期 1986.01.13
申请人 TOSHIBA CORP 发明人 KUROE YASUO
分类号 H01L21/3213;H01L21/31 主分类号 H01L21/3213
代理机构 代理人
主权项
地址
您可能感兴趣的专利