发明名称 MULTI-PROCESSOR
摘要 PURPOSE:To simplify a circuit constitution by inserting an identification number into the prescribed part of a data sequence from an information generating means, receiving the identification number through the terminal equipment of the front stage among those plural terminal equipments for initialization and producing a new identification number to transfer it to the terminal equipment of the next stage. CONSTITUTION:The decoders 3A-3I serving as terminal equipments are connected in series to a controller 1 serving as an information generating means, i.e., a center. Then an ID number is put into the prescribed area of the data sequence sent from the controller 1. The decoder 3A of the 1st stage receives the ID number from the controller 1 and is initialized. At the same time, the decoder 3A increases the received ID number to produce a new ID number and transfers it to the decoder 3B. Thus the decoder 3B receives the new ID number and is initialized and at the same time increases the received ID number to produce a new ID number and transfers it to the decoder 3C. Thereafter the same operations are repeated with decoders 3C-3I respectively.
申请公布号 JPS62163164(A) 申请公布日期 1987.07.18
申请号 JP19860004763 申请日期 1986.01.13
申请人 SONY CORP 发明人 NAKAGAWA YUTAKA;SUGA RYOICHI;WATANABE YOSHIMI
分类号 G06F15/16;G06F15/177;G06T1/00;G09G1/00;G09G5/12;H04N5/68 主分类号 G06F15/16
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