发明名称 |
TESTING SYSTEM FOR MULTIPROCESSOR SYSTEM |
摘要 |
PURPOSE:To make a controlling part changeable which accesses an I/O device in the unit of I/O-instruction by setting a lock control flag and a lock address in an I/O control table, and providing a priority processing function in a scheduler. CONSTITUTION:The lock control flag part 312 in the I/O-control table 31-36 has an area of one byte, and in this area, an 'FF' is set with a 16-ary value at the time when either one of controlling parts 11-14 collates to or writes in the said table. The lock address part 311 has an area of two bytes. When the part 312 is in 'FF' with 16-ary value i.e. the said table is in a locked state, the address of the one of the parts 11-14 that locked the part 312 is set in the said area of the part 311. The priority processing part 21 in the scheduler 2 gives priority to the controlling parts issuing an I/O-instruction in the order of their arrivals.
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申请公布号 |
JPS62162146(A) |
申请公布日期 |
1987.07.18 |
申请号 |
JP19860003330 |
申请日期 |
1986.01.10 |
申请人 |
HITACHI LTD;HITACHI COMPUT ENG CORP LTD |
发明人 |
TAKEMURA SATOSHI;TAKESUE HATACHIKA;FUKUOKA KOHEI;TAMARU HISASHI |
分类号 |
G06F15/16;G06F11/22;G06F11/267;G06F11/273;G06F15/177 |
主分类号 |
G06F15/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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