| 摘要 |
<p>PURPOSE:To make it possible to perform high speed general-purpose coordinates conversion generating no omission of an address, by a simple circuit constitution wherein a ROM, a reading means, an addition means, a reversible counter and a quadrant detection means etc. are provided. CONSTITUTION:FF1, an angle counter 2, ROM3 corresponding to the output value theta from the counter 2 and receiving writing in a form substituted with an integer and an adder circuit 4 constituted of 8 bits adding value Xh inputted to both input terminals thereof and the addition value immediately before said value are provided. Because the output values 0, 1 of FF1 are guided to an adder circuit 6, Xh and Xh+1 are alternately employed as the input values of the circuit 6 at every one revolution of an antenna. A latch circuit 5 latches the addition value by a clock pulse. Therefore, when the added value at a certain moment, for example, i.Xh is latched by the next clock pulse to be returned to the input side of the circuit 4, (i+1).Xh is outputted. At a moment when a calculated value reaches 256 or exceeds the same, a coincidence pulse is generated by the circuit 4. Further, a reversible counter 6 and a quadrant detection circuit 7 are provided to perform coordinates conversion generating no omission of an address.</p> |
