发明名称 FAULT DETECTION CIRCUIT FOR SUBSEQUENT SYNCHRONIZATION TYPE TRANSMISSION EQUIPMENT
摘要 PURPOSE:To detect a data fault by extracting a frame pattern signal in a reception data together with a clock signal at a reception section and comparing the signal with a frame pattern signal generated by the reception section. CONSTITUTION:A comparison section 6 between a reception frame pattern signal 16 sent from a reception section 1 and a transmission frame pattern signal 24 generated by a transmission section 2 and a clock detection section 9 are provided. Then the signal 16 is extracted from a reception data signal 11 and the signal 24 is generated synchronously with a clock signal 14 and when the signal 11 is interrupted, the comparison section 6 detects the dissidence between the signals 16 and 24. Further, the detection section 9 detects the interruption of the reception clock signal. Thus, both the clock interruption and the data signal interruption are detected.
申请公布号 JPS62160833(A) 申请公布日期 1987.07.16
申请号 JP19860002968 申请日期 1986.01.10
申请人 FUJITSU LTD 发明人 KAJIWARA SHINJI;FUKUSHIMA TAKEO;NAKAYOSHI MASASHI
分类号 H04J3/14 主分类号 H04J3/14
代理机构 代理人
主权项
地址