发明名称 UN COMBINADOR DE RELOJ REDUNDANTE
摘要 <p>A redundant clock combiner device includes a clock selecting latch that recovers a clock signal even if both externally supplied clocks fail. The clock selection occurs, and an output clock provided, even if the non-prioritized clock signal is restored before the prioritized clock signal.</p>
申请公布号 ES553909(D0) 申请公布日期 1987.07.16
申请号 ES20090005539 申请日期 1986.04.11
申请人 STANDARD ELECTRICA,S.A. 发明人
分类号 H03K5/19;H03K17/693;(IPC1-7):H03K19/003;H03K19/20 主分类号 H03K5/19
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