发明名称 BUS CONTROL SYSTEM
摘要 PURPOSE:To reduce the difference of response time by providing a setting means which makes the set time of the bus busy state longer than a prescribed time when the bus use rate is lower than a certain value. CONSTITUTION:A program of OS calculates the time of setting to the idle waiting state and the time of release by interrupt to calculate the busy rate of a computer, namely, the bus use rate per unit time (one minute or the like). A set value based on the use rate is set/reset to a setting means 11 (delay mode latch), which extends the time of the output of the bus busy state outputted by a bus controller in accordance with the calculated value or if this value is smaller than a prescribed value, by a diagnosis instruction. A bus controller 10 sets the time of the bus busy state by the value set to the means 11. Thus, the bus capacity is degraded when the processing load of the computer is light, and the difference of response time to terminals accompanied with the variance of the processing load of the computer is reduced.
申请公布号 JPS62160560(A) 申请公布日期 1987.07.16
申请号 JP19860001543 申请日期 1986.01.08
申请人 MITSUBISHI ELECTRIC CORP 发明人 NAKAMURA SHUNICHIRO;YAMASHITA YOJI
分类号 G06F13/20 主分类号 G06F13/20
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