| 摘要 |
A polycrystalline silicon gate (6) is manufactured on a substrate (2), then a chemical vapor deposition (CVD) oxide (14, 18) applied, covering the sidewalls (10, 12) of each of the gates (6),. An ion implantation step is then carried out to implant source and drain regions (22, 24) whose proximate edges (26, 30) are not aligned with the edges of the gate (6), due to the masking effect of the sidewall portion of the CVD oxide. Thereafter, the CVD oxide is selectively removed for those FET device locations (A) where an active FET device is desired to be formed, i.e. the ROM/PLA is personalized. Those locations are then ion implanted for source and drain extensions (34, 38) which are aligned with the edges of the gate (6). The process enables a significantly reduced turnaround time for personalizing ROMs or PLAs which contain FET memory devices. The FETs have a shorter channel length, higher breakdown voltage characteristic, an almost zero channel hot electron effect, and a lower gate-to-source/drain diffusion overlap capacitance than most other FET read only memory devices. |
