| 摘要 |
PURPOSE:To improve the control efficiency for direct memory access by switching the control stages in response to the data transfer speed. CONSTITUTION:When a DMAC device 3 selects one of I/O devices 5-1-5-4 by means of a stage identification flag 4, the corresponding stage identification signal lines 24-1-24-4 are selected. A stage switching part 11 selects a low-speed I/O exclusive stage 12 or a high-speed I/O exclusive stage 13 for control of those I/O devices 5 according to the value of a stage switching signal line 23. Then the stage 12 or 13 works in synchronization with the clock given from a clock signal line 25 and then returns to a waiting stage stage 14 when a DMA start signal line 26 is equal to '1'.
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