发明名称 FRAME SYNCHRONIZING DETECTION CIRCUIT
摘要 PURPOSE:To improve the overhead of a signal quantity of a frame pattern with respect to a transmission data quantity and a mean asynchronizing duration time characteristic by dividing the frame constitution on a transmission line into the unit of sub frames, inserting the frame pattern to a head bit of each sub frame scatteringly so as to apply synchronization detection. CONSTITUTION:One frame is divided into N-set of sub frames, each sub frame is constituted in the unit of M-bit to attain the constitution of one frame (NXM) bits and the frame bit is inserted to the head bit of each sub frame. The frame pattern inserted to the head bit of each sub frame is a cyclic code comprising 1 word N-bit generated by an optional generation polynomial. Thus, the quotient between the code polynomial using 1 word N-bit extracted from one series of the signal separated by using the property of the cyclic code as the coefficient and the generation polynomial is calculated to detect the frame pattern thereby ensuring the sub frame synchronization. Simultaneously, the 1 word N-bit being the coefficient of the code polynomial is retrieved to detect the head of the sub frame thereby ensuring the frame synchronization quickly.
申请公布号 JPS62159933(A) 申请公布日期 1987.07.15
申请号 JP19860002446 申请日期 1986.01.09
申请人 NEC CORP 发明人 YOSHIDA TOKUO
分类号 H04J3/06;H04L7/08 主分类号 H04J3/06
代理机构 代理人
主权项
地址