| 摘要 |
<p>PURPOSE:To attain sure data sampling by synchronizing a generated sampling clock with a framing code. CONSTITUTION:A pulse FP is inputted to a clear terminal of a 1/5 frequency division circuit 7, where a signal 5ck having a frequency being 5 times that of a sampling clock is inputted and a pulse whose duty is 1/5 and whose frequency is coincident with the frequency of the sampled clock ck is outputted. Thus, the pulse rising later than the timing of the pulse FP is outputted from the 1/5 frequency division circuit 7 and the phase of the output pulse is deviated from the phase of the pulse FP by 2pi/5 of the frequency of the sampled, clock ck or its multiple. Then the pulse is used as a bit synchronizing siggnal and the data is sampled by a data extraction circuit 8. Thus, the data is sampled in the timing retarded at least by 2pi/5 from the tip and the sampling is ensured.</p> |
