| 摘要 |
<p>PURPOSE:To ensure the stable selection of an address by detecting the variation of an address input given to an address input circuit through an address shift detecting circuit and delivering a pulse having the width of time corresponding to said variation of the address input from a logical circuit to select normally an address output. CONSTITUTION:An external address signal supplied to a point A1 is delivered to a point D1 via an NOR circuit 22 and an inverter 23. An address shift detecting circuit 37 detects the variation of the signal delivered to the point D1 and delivers a pulse having the width corresponding to the delay time obtained by a delay circuit 36 to a point O1. The pulse at the point O1 restores a high-level in time t02 after an external address is supplied to the point A1. This time is coincident inevitably and approximately with an elapsed time for delivering the address signal to points G1 and H1. The pulse applied to the point O1 is delivered to a point Q1 as a synchronizing signal for the reset of an address signal via an NAND circuit 34 and an inverter 35. Then the time t03 during which the synchronizing signal restores the high-level at the point Q1 is delayed by controlling the dimensions of a transistor which constitutes the circuit 34.</p> |
