发明名称 INTEGRAL SYSTEM OF MOS TRANSISTORS CONNECTED IN PARALLEL
摘要 PURPOSE:To readily calculate a source resistance by recognizing MOS transistors connected in parallel by the connecting relation of elements, and then applying a source resistance calculating model to divided diffused layers. CONSTITUTION:Layout information of diffused layers of MOS transistors is provided as attribute parameters of the transistors. The connecting relation of a plurality of MOS transistors is extracted without source resistance in such a manner that the sources and drains are connected respectively with each other. After the plurality of MOS transistors are integrated, the source resistances of the integrated transistors are calculated by referring to the layout information of the diffused layers. Thus, the source resistance can be readily calculated.
申请公布号 JPS62159445(A) 申请公布日期 1987.07.15
申请号 JP19860000544 申请日期 1986.01.08
申请人 HITACHI LTD 发明人 NAKAMURA MAYUMI;YOKOMIZO KOICHI
分类号 H01L29/78;G06F17/50;G11C11/34;G11C11/41;H01L21/82 主分类号 H01L29/78
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