| 摘要 |
PURPOSE:To obtain a bipolar CMOS structure semiconductor element having high integration without latchup by providing N<+> type and P<+> type regions which suppress the operation of a parasitic PNP transistor, and suppressing the number of heat treatments. CONSTITUTION:After an N<+> type buried diffused layer 2 is formed on a P-type substrate 1, a P<+> type buried separated region 15a P<+> type buried island region 15b and a P<+> type buried region 15c are simultaneously formed. Then, an epitaxial layer 3 is formed, an island region 4 is formed, and a collector leading region 6a and an N<+> type region 6b are simultaneously diffused. Then, a separating region 18a and an external base 18b are simultaneously formed. Thereafter, gates 12a, 12b, sources 13b, 14b, a base 13a, and an emitter 14a are formed. The region 6b suppresses a current amplification factor of the parasitic transistor of P-type MOS 33, and since the region 15c operates as the collector of the parasitic transistor, a latchup hardly occurs. The regions 6a, 6b are simultaneously formed to suppress the number of heat treatments to improve the integration. |
