| 摘要 |
PURPOSE:To supply a clock signal even when a fault takes place in the clock generating circuit without causing the performance deterioration or malfunction due to the difference of phases of clock signals by providing a clock generation circuit to each large scale circuit integration and controlling an output buffer to transfer the clock signal. CONSTITUTION:When a test mode signal A21 is at an L level, an L level is given to an output buffer 26 and an H level signal inverted by an inverter 22 is given to an output buffer 23. Thus, the clock generated by a clock generation circuit 2 of a large scale integrated circuit I1 is fed to the large scale integrated circuit I1 as a clock signal I3 via an input buffer 24 from the output buffer 23. Simultaneously, the clock is fed into a large scale integrated circuit II5 via an input buffer 25 in the large scale integrated circuit II5 from the output buffer 23 as a clock signal II7. On the other hand, when the test mode signal A21 is at an H level conversely, an H level is fed to an output buffer 26 and an L level signal inverted by the inverter 22 is fed to the output buffer 23. |
