| 摘要 |
To suppress quantitizing ambiguities upon digital transmission of an analog signal, a random access memory (RAM) (13) is connected at the end terminal of a digital transmission line, and has its output connected to an adder stage (15). The adder stage adds the digital value of +1 to the output from the RAM (13). The value of the digitized data word, incremented by +1, is then compared in a subsequent interrogation cycle of the value at the input to the memory and only if the deviation is greater than +/-1, a comparator, effecting the comparison, provides a "store" signal for transfer of the new value to the RAM (13). The D/A converters, only then, are changed to provide a changed output analog signal.
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