| 摘要 |
A quad-state input signal decoder 100 that decodes conventional three-state signals plus a fourth state in which the input signal 40 is at the frequency of, and synchronized with, a decode clock signal 35 in the decoder. Compared to three-state techniques, this invention achieves a one-third increase in the number of exclusively-active signals that can be communicated through a single line such as a I/O pin 41 of an integrated circuit 110.
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