Television composite video signal processing circuit

摘要

A television composite video signal processing circuit has a readout circuit for repeatedly reading out a one-field composite video signal from a disk memory. A delay circuit delays the composite video signal from the readout circuit by 1/2 of a horizontal sync signal period H, and a pedestal clamping circuit sets the pedestal levels of the composite video signals from the delay circuit and the readout circuit to a predetermined level. A signal selector alternately supplies the composite video signals from the readout circuit and the delay circuit to the pedestal clamping circuit for every other field, and a peak level correction circuit corrects the peak level of the delayed video signal in the delayed composite video signal from the delay circuit. The peak level correction circuit corrects the peak level of the delayed video signal so as to match this peak level with that of the nondelayed video signal from the readout circuit in accordance with a peak level difference between the delayed and nondelayed video signals.