| 摘要 |
PURPOSE:To shorten the period of memory refreshment by connecting a logic circuit having a constant delaying time between the output edge and the input edge of a dynamic memory unit to access successively. CONSTITUTION:Cell arrays 51 and 52 are composed by arranging serially connected dynamic memory cells 1-N, for example, 24 lines, and the reading data line of the array 51 is connected to the writing data line of the array 52 through a delaying circuit 53. Address successive access circuits 55 and 56 output a selecting signal. To respective input terminals of these circuits 55 and 56, the output of an N-ary counter 58 is supplied through a D-FF 57, a counter 58 counts, and then the circuits 55 and 56 output a selecting signal. Thus, memory units RAM 1 and RAM 2 are simultaneously accessed in parallel. By the above-mentioned constitution, even when the memory unit is serially connected and the delaying time of the whole of the memory is increased, the refreshing period is unchanged, and can be preserved shortly.
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