| 摘要 |
PURPOSE:To eliminate a latch error and a count error by preventing the generation timing of a latch signal and a counter reset signal from coinciding with the input timing of an UP/DOWN pulse to a counter. CONSTITUTION:A mouse controller had latch signals generating means 1-4 and a counter reset signal generating means 5 and 6 which generate latch signal S2 and a counter reset signal S4 in synchronism with neither of a count-up pulse UP and a count-down pulse DOWN, and consists of the 1st D flip-flop 4, logic circuits 1-3, the 2nd D flip-flop 5, and a logic circuit 6. Then, each UP/DOWN pulse synchronizes with the former half clock period of the 1st clock CLK, so it never coincides with the counter reset signal S3. A latch error and a count error are removed with the latch signal S2 and counter reset signal S3.
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