发明名称 TEST APPARATUS FOR INTEGRATED CIRCUIT WAFER
摘要 PURPOSE:To attain automation and power saving without raising cost by writing a positional information and an information on quality to a memory storage mounted into a vessel housing one or more of wafers, made to correspond to separate wafer. CONSTITUTION:A testing machine 1 selects an integrated circuit 3 to be tested formed onto a wafer 2 to be tested by a wafer handling section (not shown in the drawing), and conducts a test through a probe or the like. Quality informations, such as nondefectives and defectives, defective contents, etc., are written to a memory storage 5 substantially having nonvolatility mounted to a container 4 housing one or more of the wafers 2 to be tested after the completion of tests together with positional informations in which the integrated circuit 3 to be tested occupies on the wafers 20 to be tested. The positional informations written together with the quality informations are positioned naturally in the testing machine 1 in case of a type that the testing machine 1 directly controls the position of the wafer handling section, and the positional informations acquired in the memory storage can easily be transmitted over the testing machine 1 in case of a type that wafer handling section itself controls the position thereof.
申请公布号 JPS62155528(A) 申请公布日期 1987.07.10
申请号 JP19850296951 申请日期 1985.12.27
申请人 NEC CORP 发明人 ISHIGURO HIDEO
分类号 H01L21/66 主分类号 H01L21/66
代理机构 代理人
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