| 摘要 |
PURPOSE:To simplify a following gate circuit and decrease the number of bits of a memory by providing a higher rank memory, lower rank memory, decoder, and gate circuit, and selecting a code to be set in the memory. CONSTITUTION:The higher rank memory 1 inputs a higher digit as an address signal and outputs an encoded trigger signal 11. The decoder 3 inputs the signal 11 and outputs a trigger signal 31 and upper- and lower-limit triggerable signals 32 and 33 and the lower rank memory 2 inputs a low digit as an address signal and outputs upper- and lower-limit trigger signals 21 and 22. The gate circuit 4 inputs the signals 32 and 21 and outputs an AND signal 41, and the gate circuit 5 inputs the signals 33 and 22 and outputs an AND signal 51. Further, the gate circuit 6 which inputs the signals 31, 41, and 51 and outputs a trigger signal 61 is provided. |
