| 摘要 |
The summand decomposition circuit according to the object of the invention is an electronic circuit, by means of which 1-out-of-10 coded decimal digits are decomposed into partial summands with the values 5, 4, 2 and 1. The 1-out-of-10 coded decimal digit 9 is decomposed into the partial summands 5 and 4 in this circuit. The 1-out-of-10 coded decimal digit 8 is decomposed into the partial summands 5, 2 and 1 in this circuit. The 1-out-of-10 coded decimal digit 3 is decomposed into the partial summands 2 and 1 in this circuit. <IMAGE>
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