| 摘要 |
PURPOSE:To easily adjust a carrier leak under the condition in normal operation by inputting a signal which is obtained by utilizing a clock signal during the adjustment of a DC voltage instead of a parallel data signal. CONSTITUTION:When the carrier leak is adjusted, a switching circuit 30 is switched to the side of the 2nd logic circuit 31 for adjustment and a clock after series-parallel conversion is inputted to the logic circuit 31. The fetched clock signal is frequency-divided by two through the 1st D type flip-flop 3a into two signals A and B, which are inputted to a binary-quadruplicate converter 33. Binary-quadruplicate converters 32 and 33 output quadruplicate base band signals E and F on the basis of the input binary signals A and B, and C and D as well as in normal operation. |
