| 摘要 |
PURPOSE:To decrease a mask aligning allowance, to improve integration density, to decrease junction capacitance and to implement high speed operation, by forming an isolation insulating film, a compensating base region, an intrinsic base region and an emitter region with respect to a first mask by self-alignment, and reducing a base region. CONSTITUTION:On a semiconductor substrate 20, an embedded collector region 24 and an epitaxial layer 23 are formed. A first mask 25 is formed on a base forming region and an emitter forming region on the surface thereof. A second mask 26 having oxidation resistance property is formed on the side part of the mask 25. The surface other than the masks 25 and 26 is oxidized. An isolation insulating film 28 reaching the embedded collector region 21 is formed. Then the second mask 26 is removed, and a thin insulating film 29 is formed on the side part of the first mask 25. A first hole part 30, in which the surface of the epitaxial layer is exposed, is formed with the insulating film 29 and the isolation insulating film 28. Impurities are introduced, and a compensating base region 34 is formed. Then the first mask 25 is removed, and a second hole part 35 is formed. Impurities are introduced, and an intrinsic base region 36, which is conducted to the compensating base region 34, is formed. Impurities are introduced in the main surface part of the intrinsic base region 36, and an emitter region 38 is formed.
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