| 摘要 |
PURPOSE:To prevent the decrease in response performance even in a real time microprocessor system by having the function in which a main processor executes the bus right acquisition request even while another processor holds the bus right, by the main processor and the another processor. CONSTITUTION:While a main processor 1 executes a memory access and executes the program, when another processor 2 such as DMAC accesses the memory, the another processor asserts an HREQ and requests the bus right to the main processor. The main processor, when it is detected that the HREQ is asserted, asserts a HACK and delivers the bus right to the another processor. At such a time, respective signal pins of an address and address strobes AS and R/W' are made into a high impedance. An external processor, when it detects the low level of the HACK, knows that the main processor give up the bus right, comes to be a bus master and executes the memory access such as a DMA transfer.
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