| 摘要 |
PURPOSE:To lighten a load on software by increasing an address at the time of writing the data to an external memory, decreasing the address at the time of reading, dividing 2n bit data read from the external memory into two and replacing the output sequence to the internal memory of high-order (n) bit data and low-order (n) bit data. CONSTITUTION:The circuit is equipped with an address counter 15 to increase an address at the time of writing the data to an external memory 2 and decrease the address at the time of reading, and a bus converting circuit 16 to divide 2n bit data read from the external memory 2 into two and replace the output sequence to the internal memory of high-order (n) bit data and low- order (n) bit data. Thus, when to a CPU 1 having the input output data bus of an (n) bit, the external memory 2 having the input output data bus of 2n bits is connected, the variable length data of many digits can be read and written by one instruction to the external memory 2.
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