发明名称 BUFFER MEMORY DEVICE
摘要 PURPOSE:To shorten the data reading time out of an FIFO buffer by outputting the writing signal to be applied to a buffer to a separate register in case the number of data is equal to 0 within the buffer. CONSTITUTION:The contents of a reading pointer RP within a control circuit 14 are sent to a multiplexer 12 after reception of +1 from an adder 15. The outputs of both an input 11 and the multiplexer 12 are inputted to a multiplexer 16. Then the output of the multiplexer 16 is selected based on the signal (a) sent from a unit number detecting circuit in case >=2 pieces of data are stored in a buffer 10. While the input 11 is selected if <=1 piece of data is stored in the buffer 10. Furthermore the signal (b) is outputted from the unit number detecting circuit if >=1 piece of data is stored in the buffer 10 and then inputted to an AND circuit 18 to which the writing signal WE is inputted via an inverter 17. The output of the circuit 18 is inputted as a writing signal to a register 20 to which the output of the multiplexer 16 is inputted via an OR circuit 19.
申请公布号 JPS62154132(A) 申请公布日期 1987.07.09
申请号 JP19850294039 申请日期 1985.12.27
申请人 TOSHIBA CORP 发明人 KANESHIRO MORISHIGE
分类号 G11C7/00;G06F5/06 主分类号 G11C7/00
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