| 摘要 |
PURPOSE:To operate a floating point arithmetic at high speed by separating and fetching the code of an operand, an exponential part and a mantessa part in the floating point arithmetic through the use of a microinstruction having a mask specification field when said separating and fetching are executed by the architecture of one bus type. CONSTITUTION:Information specifying the operand in a floating register FR2 is set to the source field 11 of the microinstruction 1. Information controlling the mask logical function of a mask logic circuit 3 is set in mask control fields MSK and CTL. Then mask data is set to an immediate data field 13. Plural fetched operands (floating point data) are stored in the floating register FR2. The mask logic circuit 3 executes a logic operation, extracts the specified part in the operand, and outputs it to an internal bus 4. Since the microinstruction includes mask information in it and mask processing is executed the moment the operand is read, the mask of the operand can be quickly processed.
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