发明名称 CLOCK CONTROL CIRCUIT
摘要 <p>PURPOSE:To prevent the occurrence of the hazard, etc., when the clocks are switched by converting one of plural divided clocks having a smaller dividing ratio into another clock having the phase equal to that of the divided clock of the largest dividing ratio. CONSTITUTION:A 1/6 dividing circuit 3 outputs the normal 1/6 divided clock E since the 1/2 divided control signal F is equal to 1 when the clock switching signal G that selects the 1/6 divided clock is inputted to a 1/9 divided phase detecting and 1/6 dividing control circuit 4. While the signal F synchronous with the 1/9 divided clock C is outputted from the circuit 4 when the signal G which selects the clock C is continuously inputted to the circuit 4. Thus a 1/2 dividing circuit 8 stops its function until the 1/2 divided clock D has the same phase as the clock C and then restarts when both clocks C and D have the same phase. The circuit 8 repeats this action and the circuit 3 outputs the clock E.</p>
申请公布号 JPS62152029(A) 申请公布日期 1987.07.07
申请号 JP19850292281 申请日期 1985.12.26
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 HAYASHI SHOZO
分类号 H03K5/00;G06F1/04;G06F1/08 主分类号 H03K5/00
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