| 摘要 |
PURPOSE:To attain data processing at a high speed and also to avoid the wasteful application of arithmetic units by dividing a group >=1 pair of an arithmetic unit and a selection circuit into plural groups and giving a desired instruction to each of those divided groups. CONSTITUTION:The 1st pair of an arithmetic unit 100 and its corresponding selection circuit 210 and the 2nd pair of an arithmetic unit 101 and its corresponding selection circuit 211 form a group 200. While the 3rd pair of an arithmetic unit 102 and its corresponding selection circuit 212 and the 4th pair of an arithmetic unit 103 and its corresponding circuit 213 form another group 301. When the mode flag of a selection signal 500 is equal to 0, control circuits 400 and 401 make those units 100-103 perform the same arithmetic operations for the contents indicated by an instruction 1 in a simultaneous action mode. When the flag of the signal 500 is equal to 1, the circuit 400 gives the indication of the instruction 1 to the units in the group 300. While the circuit 401 gives an indication of an instruction 2 to the units in the group 301. |
