发明名称 PROGRAMMABLE CONTROLLER
摘要 PURPOSE:To attain the on-line editing of programs at a high speed without giving any effect to a logical decoding operation, by providing a shadow memory to store the same contents as a logic memory and changing the contents of the shadow memory. CONSTITUTION:When a request is received for change of the contents of a logic memory 1, a CPU performs the changing operations to a shadow memory 2 for insertion, addition, deletion, etc. Here a logical decoding part 3 reads out successively the memory 1 for logical decoding processing. When the change is through with the memory 2, an editing end signal 13 is supplied to a read/ write control part 4. Then the part 3 reads out successively the memory 2 for logical decoding processing in the next scan mode. In this case, the data are transferred to the memory 1 from the memory 2 via a data buffer 6. Then the contents of the memory 2 are coincident with those of the memory 1 when the logical decoding processing is through with a single scan. Thus the memory 1 is used again for the logical decoding process at and after the next scan.
申请公布号 JPS62152002(A) 申请公布日期 1987.07.07
申请号 JP19850291899 申请日期 1985.12.26
申请人 YASKAWA ELECTRIC MFG CO LTD 发明人 SHIGEOKA TORU
分类号 G06F11/28;G05B19/02;G05B19/05;G06F9/06;G06F12/16 主分类号 G06F11/28
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