发明名称 TIMING CLOCK CONTROL SYSTEM
摘要 PURPOSE:To facilitate the control of a timing clock even for a multipoint and low roll-off ratio QAM signal by using a carrier phase of the QAM signal estimated by deciding a QAM orthogonal amplitude modulation signal and a one-frequency pilot signal. CONSTITUTION:A multiplier 101 multiplies an input signal 10 with an output of an oscillator 102 of an oscillation frequency f1 to apply quasi-synchronization detection in a data MODEM receiver receiving the QAM signal of a carrier frequency f1 attended with a pilot signal of frequency f2. The output of the multiplier 101 is decided by a complex number decider 103 and a phase detector 104 extracts a carrier phase shift by the result of decision and a complex number signal before the decision. The pilot signal 20 uses the multiplier 105 and is multiplied with the output of the oscillator 106 whose oscillation frequency f2 to apply the quasi-synchronization detection. The multiplier 105 outputs the phase detector 104 are given to a phase detector 107, where the difference between phase shifts is detected and its output controls the frequency of the oscillator 108 to obtain a timing clock.
申请公布号 JPS62151055(A) 申请公布日期 1987.07.06
申请号 JP19850290780 申请日期 1985.12.25
申请人 NEC CORP 发明人 YOSHIDA ATSUSHI
分类号 H04L27/38;H04L27/00 主分类号 H04L27/38
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