| 摘要 |
PURPOSE:To generate plural interruption confirming signal s to an interruption controller without using a complicated circuit by combining an interruption confirming signal from a microprocessor with an interruption confirming signal by an output instruction by a program. CONSTITUTION:A processor 1 and an ICU 2 are connected by a data bus and an interruption requesting signal and the processor 1 and a circuit part 5 (developing part 5) to develop an I/O address are connected by an address bus and an I/O reading signal. An INTG 4 is connected to the processor 1 by an INTA- A, connected to the developing part 5 by an interruption confirming signal C (INTA-C) and the output edge is connected to the INTA terminal of the ICU 2. Thus, since the interruption confirming signal after the second time is outputted by the output instruction of a program, plural interruption confirming signals to an interrupting controller can be generated.
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