| 摘要 |
PURPOSE:To output a reset signal synchronously with an optional period of clock signal without using a latch circuit by providing the 1st and 2nd diodes storing an electric charge respectively and an inverter and releasing the timing of a reset signal by means of a clock. CONSTITUTION:When the 1st power supply Vss is 0V and the 2nd power supply VDD is fed in the timing at the 1st voltage change point T1 shown in figure A, the voltage at a connecting point N0 is 0V in the timing T1 as shown in figure C, then a level of an output terminal T1 of an inverter INV connected to the connecting point N0 rises in the timing T1 as shown in figure D. In inputting a clock CLK in the timing T2 as shown in figure B, since a diode D1 is biased forward, an electric charge is stored in the capacitor C and the level of the connecting point N0 rises in the timing T2 as shown in the figure C. When the level of the connection point N0 rises in excess of a threshold value of the inverter INV, the inverter INV rises invertingly and outputs a reset signal released synchronously with the clock shown in the figure D.
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