| 摘要 |
PURPOSE:To decrease an address comparing action while the jumping instruction is performed by a continuous address, to store the instruction of the continuous address into an instruction cue and to decrease the capacity of a cache memory by executing the instruction in an instruction cue except the time of executing the jumping instruction and executing the instruction from the cache memory only after the jumping instruction is executed. CONSTITUTION:Usually, an instruction is read from instruction cues 8-10 to an instruction register 1 by a jumping instruction identifying signal 12 except the time of executing the jumping instruction, and the instruction is always prefetched from an external part memory to the instruction cue. For several instructions after the jumping instruction is executed, instruction (5 in case of 2, 6 in case of 3 and 7 in case of 4) coincident to a prefetching address 1 are read at an instruction register 11.
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