| 摘要 |
PURPOSE:To prevent malfunction of the titled circuit due to an erroneous frame synchronization detection signal by deciding whether or not frame synchronization locking is executed normally at each frame of a digital signal and controlling the operation of a synchronizing detection means based on the result of the decision. CONSTITUTION:A window generation pulse is outputted before 1-2 symbols at the output of a reset signal of a counter is outputted from a ring counter 12. An output of a window generating circuit 14 is set to 'L' based on the window generation pulse. The set signal is inputted to a gate circuit 16, which is in standby until a frame synchronization detection signal SYNC is inputted. The frame synchronization detection signal SYNC sets an output of the window generating circuit 14 to 'H' at the same time when the ring counter 12 is reset or an error detection signal is outputted and a signal from the frame synchronization detection circuit 2 is blocked by the gate circuit 16. Through the operation above, the malfunction of the ring counter 12 due to a pseudo SYNC is blocked. |
