| 摘要 |
PURPOSE:To obtain the highly integrated dynamic type semiconductor memory storage having a large information charge accumulation capacitance, a large operational margin and a small chip area by a method wherein capacitance between polycrystalline silicons is formed in a grooved isolation region, and an opposing electrode type 2-cell/1- bit structure is integrated together with a folding type bit wire structure. CONSTITUTION:An N<+> type diffusion layer 5 is formed in a suitable region on a P-type silicon substrate 1, and this N<+> type diffusion layer 5 becomes the source and drain region of the gate transistor of each memory cell. The P-type silicon substrate, located between the N<+> type diffusion layer 5 constituting the drain region is formed and the N<+> type diffusion layer 5 constituting the source region, forms the channel region 11 of the transistor. A grooved isolation region 17 is formed on the circumference of the N<+> type diffusion layer 5 and the channel region 11, and a pair of opposing electrodes 12 and 13 are opposingly formed in the grooved isolation region 17 leading the prescribed space between them. A memory cell capacitor, namely, an information charge accumulation capacitor is formed with said opposing electrodes 12 and 13 and the capacitor insulating film 14 located between the electrodes 12 and 13. |
