| 摘要 |
PURPOSE:To quicken the data transfer by providing a static random access memory (SRAM) maintained to a chip selection state and a data buffer and applying selective control to the data buffer based on an address signal. CONSTITUTION:When address signals A0-A1 are fed to data output means SRAM1 and SRAM2 from a CPU, after an address access time specific to the SRAM elapses, data D0-Dm and Dm+1-D2m+1 are read respectively corresponding data buffers BUF1-BUF4. The time when the data buffers BUF1-BUF4 are brought into the data input/output enable state from the tri-state by gate control signals phig1-phig4 is very short in comparison with the chip select access time of the SRAM and the address access time. Thus, the timing when the data read from the means SRAM1, SRAM2 is fetched by the CPU is quickened to the utmost degree.
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