发明名称 INTEGRATED CIRCUIT
摘要 PURPOSE:To decide whether the polarity of an output signal of a connection destination is active or nonactive by providing a circuit storing the active polarity of an input signal and a polarity decision circuit of the input signal in response to the storage content. CONSTITUTION:When a reset signals is fed to an input terminal 2, a three-state buffer 3 is turned on, a signal at a terminal 1 is inputted via connection lines 6, 8 as a data a D-type FF 4. In this case, since the reset signal is fed as the clock of the FF 4, the FF is latched at the leading and when the output of the FF 4 goes to '1' when the nonactive polarity of the terminal 4 is logical '1' and the output is '0' when the output is logical '0'. After the end of reset, the output of the FF 4 and the input signal to the terminal 1 are inputted to an exclusive NOR circuit 5 after the end of reset and the polarity of the input signal is inverted. Thus, the information relating to the nonactive polarity after storage is dissident at the reset only, then the signal of an input signal connection line 10 represents the active polarity to discriminate the polarity of the output signal of connection destination.
申请公布号 JPS62149220(A) 申请公布日期 1987.07.03
申请号 JP19850289423 申请日期 1985.12.24
申请人 NEC CORP 发明人 UTSUKI TSUTOMU
分类号 H03K19/00 主分类号 H03K19/00
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